|title ||Digital VLSI Design|
|arbic title |
|prequisites ||EC432, CC216 |
|credit hours ||3|
|Describtion/Outcomes ||Design of VLSI digital circuits, Stick diagrams, design rules, CAD system, speed and power considerations, floor planning, layout techniques|
|arabic Describtion/Outcomes |
|objectives ||To introduce students to the basic principles of designing a digital VLSI chip and using CAD tools and to simulate the design.|
|arabic objectives |
|ref. books ||R. L. Geiger, P. E. allen and N. R. Strader, ?VLSI Design Techniques for Analog and Digital Circuits?, McGraw-Hill, 1990.rnP. Allen, D. Holberg, ?CMOS Analog Circuit Design? , 2nd ed., Oxford University Press, 2002.Glasler, Dobberpuhi, ?The Design & Analysis of VLSI Circuits?, AW, 1988.rn|
|arabic ref. books |
|textbook ||N. Weste, K. Eshraghian, ?Principles of CMOS VLSI Design?, 2nd ed., Addison Wesley, 1993.|
|arabic textbook |
|objective set |
|content set |
||MOS Transistor Theory (1), Introduction to NMOS Enhancement Transistor, PMOS, enhancement Transistor, Threshold Voltage, Body Effect
||MOS Transistor Theory (2), MOS Basic d.c. Equations, Second Order Effects, Threshold Voltage ? Body Effect, Sub threshold Region, Channel-length Modulation, Mobility Variation, MOS Models, Small Signal a.c. Characteristics.
||MOS Transistor Theory (3), The Complementary CMOS Inverter ? DC Characteristics, σn/ σp ratio, Noise Margin, The CMOS Inverter as an amplifier, Static Load MOS Inverters, The Pseudo-nMOS Inverter, Saturated Load Inverter, The Cascode Inverter, The Transmission Gate.
||Stick Diagrams: Introduction to Stick Diagrams, Stick Diagramming Rules, Color Codes, Design Rules.
||CAD Tools, Introduction to CAD, SPICE Modeling, Visual Editor Interfacing, Introduction to MAGIC Program.
||Speed and Power Considerations (1), Introduction to Resistance Estimation, Resistance of nonrectangular regions, Contacts and Via Resistance, Capacitance Estimation, MOS-Capacitor Characteristics, MOS Device Capacitance, Diffusion (source/drain) Capacitance, SPICE Modeling of MOS Capacitance, Routing Capacitance, Distributed RC Effects, Capacitance Design Guide, Inductance.
||Speed and Power Considerations (2), Switching Characteristics, Analytical Delay Models, Fall Time, Rise Time, Delay Time, Empirical Delay Models, Gate Delays, Further Delay Topics, Input Waveform Slope, Input Capacitance, Body Effect, Exam (1).
||Speed and Power Considerations (2), Power Dissipation, Static Dissipation, Dynamic Dissipation, Short-Circuit, Dissipation, Total Power Dissipation, Power Economy.
||Floor Planning (1), Placement and Routing for Standard Cells, Placement and Routing for Gate Array.
||Floor Planning (2), Variable Size Blocks: Placement and Routing, Channel Routing, Routing Algorithms.
||Layout Techniques and Design Rules (1), Layout of Standard Cells, Layout of Gate Arrays, Layout of Variable Size Blocks
||Layout Techniques and Design Rules (2), Layout Design Rules ? Minimum Spacing- Minimum Feature Dimensions Design Rule Checks, Exam (2)
||Design Techniques for Testability, Design for Testability, Ad-Hoc Testing, Scan-Based Test Techniques, Self-Test Techniques.
||VLSI Basic Building Blocks, CMOS Complementary Logic - Inverter, NAND, NOR, XOR, BiCMOS - Inverter, NAND, NOR, XOR, Other CMOS Logic Structure - Inverter, NAND, NOR, XOR
||Revision, Highlights on Special issues.