Course

code	CC723E
credit_hours	3
title	Digital Design for Stability and Testability
arbic title
prequisites
credit hours	3
Description/Outcomes	This course will cover the practical implementation of VHDL language in depth and explains how to use it to describe complex combinational and sequential logic circuits. Functional verification of VHDL designs is accomplished using a logic simulator. It also covers the various techniques which are used to reduce the amount of input test patterns to ensure that an acceptable level of fault coverage has to be obtained. Learning Outcomes Understand how to describe a digital system using a Hardware Description Language. Model complex combinational logic in VHDL. S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design, McGraw Hill, 2000 Understand the HDL design flow including synthesis and place/route and its effect on timing. Perform logic simulations on your digital designs (pre and post synthesis) Digital systems Testing and Fault detection.
arabic Description/Outcomes
objectives	To learn how to implement design digital systems, from specification and simulation to construction and debugging. To learn how to use modern laboratory test equipment, including logic analyzers and oscilloscopes To understand the limitations and difficulties in modern digital design, including wiring constraints, high-speed, etc. To design, construct, test, and debug a moderate-scale digital circuit. Understand the concept of digital system stability.
arabic objectives
ref. books	rn Parag K, Lala, An Introduction to Logic Circuit testing, Morgan & Claypool, 2009 S. Palnitkar, VHDL Design Representation and Synthesis (Second Edition), Prentice Hall, 2000 S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design, McGraw Hill, 2000 Z. Navabi, VHDL: Analysis and Modeling of Digital Systems, McGraw Hill (Second Edition), 1998 J. R. Armstrong, VHDL Design Representation and Synthesis (Second Edition), Prentice Hall, 2000
arabic ref. books
textbook
arabic textbook
objective set
content set

Course Content

content serial	Description
1	Review of basic digital-logic design
2	Hardware description languages (HDLs, esp. VHDL) Analysis, Modeling and Partitioning for Logic Synthesis and VHDL Coding
3	Fault Detection
4	Design for Testability, Built-In Self-Test, and Fault Tolerance